With the design trend in electronic devices is toward lighter, smaller, thinner but more functional devices with performance requirements continuing to increase, device manufacturers increasingly need specialty integrated circuit (IC) solutions for allowing billions of miniature electronic components to be densely packed in a small area. Thus, device manufacturers come up with innovative packaging techniques for embedding electronic components in a substrate while allowing shorter traces between the electronic components and the substrate. In addition, the layout area is increased by the use of built-up technique as the technology advances for achieving lighter, smaller, thinner and more functional high-performance devices.
Generally, most high-end chips are packaged by flip chip (FC) process, especially by a chip scale package (CSP) process, as those high-end chips are primarily being applied in smart phones, tablet computers, network communication devices, and notebook computers, whichever is generally operating under high-frequency and high-speed condition and required to be packed in a thin, small and light-weighted semiconductor package. As for the carrier for packaging, the popular design nowadays includes: small pitches between lines, high density, thin-type design, low manufacture cost, and high electrical characteristic.
Please refer to FIG. 1, which shows a conventional fiberglass substrate packaging structure. In FIG. 1, the fiberglass substrate packaging structure with molded interconnection system 1 includes a bump bonding structure 10A and a wire bonding structure 10B, and is structured for allowing a conductive pillar layer 110A to be embedded inside a fiberglass substrate 100A, whereas the fiberglass substrate 100A can be a bismaleimide triazine (BT) substrate or a FR-5 substrate. In addition, there is further a protection layer 120A and conductive elements 140A being disposed on the conductive pillar layer 110A while simultaneously allowing the bump bonding of certain internal components 130A to be disposed on the conductive pillar layer 110A, and a molding compound layer 150A to be disposed on the fiberglass substrate 100A. Similarly, the other conductive pillar layer 110B is also embedded inside the other fiberglass substrate 100B, and the fiberglass substrate 100B can be a bismaleimide triazine (BT) substrate or a FR-5 substrate. Furthermore, there is further a protection layer 120B and conductive elements 140B being disposed on the conductive pillar layer 110B while simultaneously allowing the wire bonding of certain internal components 130B to be disposed on the conductive pillar layer 110B, and a molding compound layer 150B to be disposed on the fiberglass substrate 100B.
It is noted that the aforesaid fiberglass substrate packaging structure with molded interconnection system 1 is formed by forming through mold via (TMV) on the molding compound layer 150A of the bump bonding structure 10A so as to be used for enabling the conductive elements 140A to connect electrically to conductive elements 140B of the wire bonding structure 10B.
However, the aforesaid conventional fiberglass substrate packaging structure is very costly for using a fiberglass substrate as its substrate and the thin-type fiberglass substrate can be easily deformed and wrapped. The conventional substrate including fiberglass will increase the difficulty of processing for laser via so that it cannot fit the need of fine pitch, and therefore make the wiring more troublesome; and as the blind/buried vias in the aforesaid multi-layered metal laminated structure are formed by the repetition of a laser via method, such repetition can be a complex and time consuming process. Since the electrical connections between the plural bonding structures in the package structure are achieved through the TMV whereas such TMV should be fabricated by the use of a laser via process, the whole package fabrication process can be very costly.